Robust Demand for Advanced Packaging Driving Lithography Market Says The Information Network

ALLENTOWN, Pa. - June 2, 2016 - PRLog -- Lithography equipment for advanced packages that house state-of-the-art semiconductors have technical and cost requirements that cannot be met by EUV or DUV equipment. A robust demand for advanced packages for mobile and IoT will drive the equipment market, according to the entitled, "Flip Chip/WLP Manufacturing And Market Analysis," recently published by The Information Network, a New Tripoli, PA-based market research company.

Lithography tools are used for patterning Advanced Packages that house leading edge ICs. The semiconductor industry is moving toward advanced packaging, as new products from smartphones, mobile devices, and the IoT demand higher integration of features in an innovative form factor. Fan-out wafer level packaging (FO-WLP), fan-in wafer level chip scale packaging (WLCSP), flip-chip and 2.5D/3D packaging represent only some of the approaches used today.

"The advanced package lithography sector was valued at $195 million, but is growing at four times the rate of mainstream IC lithography, 18.6% versus only 4.8%," noted Dr. Robert Castellano, president of The Information Network. "Ultratech led the $195 million advanced packaging lithography market in 2015. Between 2014 and 2015, the company's revenues grew 57.0%. but Rudolph Technologies' revenues grew an astounding 287.7%."

The report details an analysis of the different types of steppers used in advanced packaging from each of the lithography suppliers listed in the chart.


According to the report, advanced packaging lithography confronts a set of challenges that are unique to the application, meaning that an EUV or DUV mainstream lithography tool would not work. These include:

·      Feature sizes range from micrometers to hundreds of micrometers and often require photoresist or dielectric layers much thicker than those found in front- end photolithography.

·      The lithography system must be able to supply enough energy to activate the photosensitive material (e.g. resist, polyimide, dielectric, etc.), while maintaining focus throughout the thickness to precisely control critical dimensions (CD) and sidewall profiles.

·      A wide variety of substrates are used, including silicon wafers, thinned wafers, reconstituted wafers (in which separated die are embedded in a polymer compound), glass and more.

·      The substrates may exhibit several millimeters of warp, and there may also be significant die-to-die and within-die topography resulting from embedding and bumping processes.

·      In addition to warp of materials, systems need to be able to manage dimensional instability due to process induced stresses.

Link: http://www.theinformationnet.com

Keywords: semiconductors, ICs, lithography

Contact: Dr. Robert Castellano, (610)737-7596